Three-dimensional memory device including trench-isolated memory planes and method of making the same
AssigneeSanDisk Technologies LLC
InventorTeruo OKINA
Life of this patent
Estimating the term…
Abstract
A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally extend between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside insulating material portion that provides electrical isolation between the three-dimensional memory planes.
Claims20
A three-dimensional memory device, comprising:
- a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, first memory openings vertically extending through a respective one of the first alternating stacks and filled with first memory opening fill structures including a respective first vertical semiconductor channel and first memory film, and first bit lines overlying the first alternating stacks, extending over an area of the first alternating stacks, and electrically connected to a respective subset of the first vertical semiconductor channels;
- a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines, second memory openings vertically extending through a respective one of the second alternating stacks and filled with second memory opening fill structures including a respective second vertical semiconductor channel and second memory film, and second bit lines overlying the second alternating stacks, extending over the area of the second alternating stacks and electrically connected to a respective subset of the second vertical semiconductor channels and electrically isolated from each of the first vertical semiconductor channels and the first bit lines;
- and
- an inter-array backside trench laterally extending along a word line direction between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside trench fill structure comprising an inter-array backside insulating material portion.
A method of forming a three-dimensional memory device, comprising:
- forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over a substrate;
- forming memory openings through the vertical alternating sequence;
- forming memory opening fill structures in the memory openings, wherein the memory opening fill structures comprises a respective vertical semiconductor channel and memory film;
- dividing the vertically alternating sequence into a first memory plane comprising first alternating stacks of first insulating layers and first sacrificial material layers that are laterally spaced apart by first backside trenches, and a second memory plane comprising second alternating stacks of second insulating layers and second sacrificial material layers that are laterally spaced apart by second backside trenches, wherein the first alternating stacks and the second alternating stacks are laterally spaced apart by an inter-array backside trench, and wherein a first subset of the memory opening fill structures vertically extends through a respective one of the first alternating stacks and a second subset of the memory opening fill structures vertically extends through a respective one of the second alternating stacks;
- replacing the first sacrificial material layers and the second sacrificial material layers with first word lines and second word lines, respectively;
- and
- forming first bit lines and second bit lines over the first alternating stacks and the second alternating stacks, wherein the first bit lines are electrically connected to a respective subset of the first vertical semiconductor channels and electrically isolated from the second vertical semiconductor channels, and second bit lines are electrically connected to a respective subset of the second vertical semiconductor channels and electrically isolated from the first vertical semiconductor channels.
Dependencies are inferred from the claim text.