Semiconductor device including ferroelectric layer and method of manufacturing the same

A semiconductor device comprising:

• a substrate;
• a bit line structure and a source line structure each extending in a direction perpendicular to a surface of the substrate;
• and
• a plurality of unit cell structures electrically connected to the bit line structure and the source line structure,
• wherein each of the plurality of unit cell structures comprises:
• a semiconductor layer disposed on a plane parallel to the surface of the substrate and in contact with the bit line structure and the source line structure;
• a first ferroelectric layer disposed on a first surface of the semiconductor layer;
• and
• a first gate electrode layer disposed on the first ferroelectric layer and spaced apart from the bit line structure and the source line structure,
• wherein the plurality of unit cell structures are disposed to be spaced apart from each other in a direction perpendicular to the surface of the substrate.

A method of manufacturing a semiconductor device, the method comprising:

• providing a substrate including a base insulating layer;
• forming a first stack structure on the base insulating layer, the first stack structure including first and second insulating layers disposed to be spaced apart from each other in a direction perpendicular to a surface of the substrate, and a sub-structure disposed between the first and second insulating layers, wherein the sub-structure includes a semiconductor layer and at least one sacrificial layer;
• selectively etching the first stack structure on the base insulating layer to form a second stack structure including a first trench and a first recess space, the first trench being formed to expose the base insulating layer, and the first recess space being formed by selectively etching the at least one sacrificial layer in the first trench;
• forming a third stack structure including a plurality of material layers disposed in the first recess space of the second stack structure, the plurality of material layers including an interfacial insulating layer disposed on the semiconductor layer, a ferroelectric layer to cover at least the interfacial insulating layer, and a gate electrode layer disposed on the ferroelectric layer;
• forming a fourth stack structure including a bit line structure disposed in the first trench of the third stack structure on the base insulating layer;
• selectively etching the fourth stack structure on the base insulating layer to form a fifth stack structure including a second trench exposing the base insulating layer, the second trench exposing the semiconductor layer, the interfacial insulating layer, the ferroelectric layer, the gate electrode layer, and the first and second insulating layers on a sidewall surface of the second trench;
• and
• forming a sixth stack structure including a source line structure disposed in the second trench of the fifth stack structure.