Semiconductor devices

A semiconductor device, comprising:

• a substrate including a cell array region, a first peripheral region, and a second peripheral region;
• memory cells on the cell array region of the substrate;
• trenches in the first and second peripheral regions of the substrate;
• an isolation structure filling each of the trenches, the isolation structure including an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked;
• a channel layer in the first peripheral region of the substrate, the channel layer including silicon germanium;
• a first gate structure on the channel layer, the first gate structure including a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked;
• and
• a second gate structure on the second peripheral region of the substrate, the second gate structure including a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked,
• wherein the inner wall oxide pattern and the nitride liner are conformal on surfaces of each of the trenches, the nitride liner protruding above upper surfaces of the inner wall oxide pattern and the filling insulation pattern.

A semiconductor device, comprising:

• a substrate including a cell array region, a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region;
• memory cells on the cell array region of the substrate;
• trenches on first to fourth peripheral regions of the substrate;
• an isolation structure filling each of the trenches, the isolation structure including an inner wall oxide pattern, a nitride liner, and a filling insulation pattern sequentially stacked;
• a channel layer on the first peripheral region of the substrate, the channel layer including silicon germanium;
• a first gate structure on the channel layer, the first gate structure including a first interface insulation pattern, a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked;
• a second gate structure on the second peripheral region of the substrate, the second gate structure including a second interface insulation pattern, a second high-k dielectric pattern, a second P-type metal pattern, and a second N-type metal pattern sequentially stacked, and a thickness of the second interface insulation pattern being greater than a thickness of the first interface insulation pattern;
• a third gate structure on the third peripheral region of the substrate, the third gate structure including a third interface insulation pattern, a third high-k dielectric pattern, and a third N-type metal pattern sequentially stacked;
• and
• a fourth gate structure on the fourth peripheral region of the substrate, the fourth gate structure including a fourth interface insulation pattern, a fourth high-k dielectric pattern, and a fourth N-type metal pattern sequentially stacked,
• wherein the nitride liner is conformal on surfaces of each of the trenches, the nitride liner protruding above upper surfaces of the inner wall oxide pattern and the filling insulation pattern, and a height of an uppermost surface of the nitride liner is substantially the same in each of the trenches.