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US 2022/0189967 A1Published application
Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsDongoh KIM, Gyuhyun KIL, Junghoon HAN, Doosan BACK
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Abstract
A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.
Claims20
A semiconductor memory device comprising:
- a substrate including a memory cell region, an active region in the memory cell region, a peripheral region, and a logic active region in the peripheral region;
- an element isolation structure between the active region and the logic active region, the element isolation structure defining the active region and the logic active region;
- an insulating layer pattern covering the active region, the insulating layer pattern including an extension portion that extends along the element isolation structure, is spaced apart from the element isolation structure, and overhangs over the element isolation structure;
- and
- a support insulating layer filling a recess space defined between the extension portion and the element isolation structure.
2 more elements
A semiconductor memory device comprising:
- a substrate including a memory cell region, an active region in the memory cell region, a peripheral region, and a logic active region in the peripheral region;
- an element isolation structure between the active region and the logic active region, the element isolation structure defining the active region and the logic active region;
- an insulating layer pattern covering the active region, the insulating layer pattern having a stacked structure in which a second insulating layer pattern is on a first insulating layer pattern extending over the element isolation structure between the active region and the logic active region;
- and
- a support insulating layer between the insulating layer pattern and the element isolation structure, wherein
- the first insulating layer pattern includes a first extension portion,
- the second insulating layer pattern includes a second extension portion,
- an extension length of the second extension portion is greater than an extension length of the first extension portion,
- each of the first extension portion and the second extension portion extend along the element isolation structure, are spaced apart from the element isolation structure, and overhang over the element isolation structure, and
- the support insulating layer fills a recess space defined between the element isolation structure and a portion of the second extension portion extends over the element isolation structure from the first extension portion.
7 more elements
A semiconductor memory device comprising:
- a substrate including a memory cell region, a plurality of active regions in the memory cell region, a peripheral region, and a plurality of logic active regions in the peripheral region,
- the substrate defining a plurality of word line trenches extending in parallel with each other in a horizontal direction across the plurality of active regions in the memory cell region;
- an element isolation structure between the plurality of active regions and the plurality of logic active regions and along between the memory cell region and the peripheral region, the element isolation structure defining the plurality of active regions and the plurality of logic active regions;
- a gate dielectric layer, a word line, and a buried insulating layer sequentially positioned in each of the plurality of word line trenches;
- an insulating layer pattern covering the plurality of active regions and the buried insulating layer, the insulating layer extending over the element isolation structure between the memory cell region and the peripheral region, and the insulating layer pattern including a first insulating layer pattern and a second insulating layer pattern on the first insulating layer pattern;
- a transistor on the logic active region, the transistor including a gate insulating layer and a gate line on the gate insulating layer, the gate insulating layer having a stacked structure of a first gate insulating layer pattern having a first thickness and a second gate insulating layer pattern having a second thickness;
- and
- a support insulating layer between the insulating layer pattern and the element isolation structure, wherein
- the first insulating layer pattern includes a first extension portion,
- the second insulating layer pattern includes a second extension portion,
- an extension length of the second extension portion is greater than an extension length of the first extension portion,
- each of the first extension portion and the second extension portion extend along the element isolation structure from over the plurality of active regions and the buried insulating layer, are spaced apart from the element isolation structure, and overhang over the element isolation structure,
- the support insulating layer fills a recess space defined between the element isolation structure and a portion of the second extension portion further extending from the first extension portion over the element isolation structure,
- a material in the support insulating layer is the same material as a material in the first gate insulating layer pattern, and
- the support insulating layer has a third thickness that is at least twice as large as the first thickness of the first gate insulating layer pattern.
12 more elements
Dependencies are inferred from the claim text.