Semiconductor device with controllable channel length and manufacturing method thereof
AssigneeKey Foundry Co., Ltd.
InventorHyun Kwang SHIN
Life of this patent
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Abstract
A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.
Claims11
A method of manufacturing a semiconductor device, the method comprising:
- forming an N-type buried layer in a substrate;
- forming a P-type deep well region and an N-type deep well region on the N-type buried layer;
- forming a P-type well region and an N-type well region on the P-type deep well region and the N-type deep well region, respectively;
- forming a gate electrode having a closed-loop in which an opening area is formed in a central region, the gate electrode overlapping the P-type well region and the N-type well region;
- forming a source region and a drain region in the P-type well region and the N-type well region, respectively;
- forming silicide layers on the source and drain regions;
- and
- forming a deep trench isolation region surrounding the silicide layers and the gate electrode,
- wherein the deep trench isolation region is formed after the silicide layers are formed on the source and drain regions, and
- wherein the deep trench isolation region is formed vertically to abut the N-type deep well region and the N-type buried layer.
A method of manufacturing a semiconductor device, the method comprising:
- forming a buried oxide layer on a substrate,
- forming an N-type buried layer on the buried oxide layer;
- forming a first insulating isolation region, a second insulating isolation region, and a third insulating isolation region on the substrate, respectively;
- forming a P-type well region and an N-type well region on the N-type buried layer;
- forming a gate electrode having a closed-loop in which an opening area is formed in a central region, the gate electrode overlapping the P-type well region and the N-type well region;
- forming a source region and a drain region in the P-type well region and the N-type well region, respectively;
- forming silicide layers on the source and drain regions;
- and
- forming a deep trench isolation region surrounding the silicide layers and the gate electrode,
- wherein the deep trench isolation region is formed after the silicide layers are formed on the source and drain regions, and
- wherein the deep trench isolation region is deeper than the first to third insulating isolation regions, and is disposed to be in direct contact with an upper surface of the buried oxide layer.
Dependencies are inferred from the claim text.