Semiconductor device with diffusion suppression and ldd implants and an embedded non-ldd semiconductor device

A method of forming a semiconductor device, comprising:

• forming a first gate dielectric of a first transistor on a substrate in an area for the first transistor;
• forming a second gate dielectric of a second transistor on the substrate in an area for the second transistor;
• forming a first gate electrode on the first gate dielectric;
• forming a second gate electrode on the second gate dielectric;
• forming a lightly doped drain (LDD) photomask over the substrate, the LDD photomask exposing the area for the first transistor and covering a second area for the second transistor;
• implanting a first dose of first conductivity type dopants into a semiconductor material of the substrate adjacent to the first gate electrode, wherein the first dose of first conductivity type dopants is blocked from the semiconductor material under the first gate electrode by the first gate electrode and is blocked from the semiconductor material in an area for the second transistor by the LDD photomask;
• implanting a diffusion suppression species into the semiconductor material adjacent to the first gate electrode, wherein the diffusion suppression species is blocked from the semiconductor material under the first gate electrode by the first gate electrode and is blocked from the semiconductor material in the area for the second transistor by the LDD photomask;
• subsequently removing the LDD photomask;
• heating the semiconductor material to activate the first dose of first conductivity type dopants to form an LDD implant region;
• implanting a second dose of the first conductivity type dopants into the semiconductor material adjacent to first sidewall spacers at edges of the first gate electrode and adjacent to second sidewall spacers at edges of the second gate electrode.

A semiconductor device, comprising:

• a semiconductor device substrate including a semiconductor material;
• a first transistor of a first polarity, the first transistor including:
• a first gate structure including a first gate electrode on a first gate dielectric over the semiconductor material;
• a first source/drain in the semiconductor material adjacent to the first gate structure, the first source/drain region having a first conductivity type, the first source/drain region being laterally separated from the first gate electrode;
• and
• a first source drain extension region in the semiconductor material including;
• a lightly doped drain (LDD) implant region having the first conductivity type, the LDD implant region extending from the first source/drain region to a first location under the first gate electrode;
• and
• a diffusion suppression region including a diffusion suppression species, the diffusion suppression region extending from the first source/drain region under the first gate electrode;
• a second transistor of a second polarity, oriented perpendicular to the first transistor, the second transistor including:
• a second gate structure including a second gate electrode on a second gate dielectric over the semiconductor material;
• and
• a second source/drain region in the semiconductor material adjacent to the second gate structure, the second source/drain region having the first conductivity type, the second source/drain region being laterally separated from the second gate electrode;
• and
• a second source/drain extension region in the semiconductor material including:
• a lightly doped drain (LDD) implant region having the first conductivity type, the LDD implant region extending from the second source/drain region to a second location under the second gate electrode;
• and
• a diffusion suppression region including a diffusion suppression species, the diffusion suppression region extending from a second source/drain region under the second gate electrode;
• a third transistor of the first polarity, the third transistor including:
• a third gate structure including a third gate electrode on a third gate dielectric over the semiconductor material;
• and
• a third source/drain region in the semiconductor material adjacent to the third gate structure, the third source/drain region having the first conductivity type, the third source/drain region extending to a third location under the third gate electrode;
• and
• a fourth transistor of the first polarity, oriented perpendicular to the third transistor, the fourth transistor including:
• a fourth gate structure including a fourth gate electrode on the fourth gate dielectric over the semiconductor material;
• and
• a fourth source/drain region in the semiconductor material adjacent to the fourth gate structure, the fourth source/drain region having the first conductivity type, the fourth source/drain region extending to a fourth location under the fourth gate electrode;
• wherein:
• the third transistor and the fourth transistor are free of a diffusion suppression region;
• and
• the third transistor and the fourth transistor are free of an LDD implant region;
• and
• average concentrations of first conductivity type dopants in the first source/drain region, the second source/drain region, the third source/drain region and the fourth source/drain region are equal.