Nitride semiconductor device

A nitride semiconductor device, comprising:

• an insulating substrate, wherein the insulating substrate comprises a first surface and a second surface;
• a substrate over the first surface of the insulating substrate, wherein the substrate comprises a first surface and a second surface;
• a first lateral transistor over a first region of the substrate, wherein the first lateral transistor comprises:
• a first nitride semiconductor layer formed over the substrate;
• and
• a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer, wherein the first gate electrode is between the first source electrode and the first drain electrode, and the first source electrode extends over the first gate electrode and toward a direction opposing to the first drain electrode, and at least a portion of a first passivation layer configured to cover the first gate electrode is between the first gate electrode and the first source electrode;
• a second lateral transistor over a second region of the substrate, wherein the second lateral transistor comprises:
• a second nitride semiconductor layer formed over the substrate;
• and
• a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer, wherein the second gate electrode is between the second source electrode and the second drain electrode, and wherein the second source electrode extends over the second gate electrode and toward a direction opposing to the second drain electrode, and at least a portion of a second passivation layer configured to cover the second gate electrode is between the second gate electrode and the second source electrode;
• a separation trench formed over a third region, wherein the third region is between the first region and the second region;
• a first interlayer insulating layer formed over the first source electrode and the second source electrode;
• and
• a second interlayer insulating layer formed in the separation trench, wherein the separation trench extends along a thickness direction of the insulating substrate and stops at a position in the insulating substrate, and the first lateral transistor and the second lateral transistor are electrically connected via a wiring over the second interlayer insulating layer in the separation trench.