Devices including control logic structures, and related methods
AssigneeMicron Technology, Inc.
InventorsKurt D. Beigel, Scott E. Sills
Life of this patent
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Abstract
A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
Claims20
A device, comprising:
- a first deck structure comprising a first control logic level comprising control logic including one or more of decoders, multiplexers, sense amplifiers, inverters, NAND gates, and additional pass gates, the first control logic level comprising:
- a first sub-deck structure comprising first vertical transistors;
- and
- a second sub-deck structure vertically overlying the first sub-deck structure and comprising second vertical transistors;
- and
- at least a second deck structure vertically overlying the first deck structure and comprising a second control logic level comprising additional control logic including at least one of additional decoders, additional multiplexers, additional sense amplifiers, additional inverters, additional NAND gates, and additional pass gates.
A device, comprising:
- a first deck structure comprising a first control logic level, the first control logic level comprising:
- a first sub-deck structure comprising first vertical transistors;
- a second sub-deck structure vertically overlying the first sub-deck structure and comprising second vertical transistors;
- and
- a gate contact electrically connecting gate electrodes of the first vertical transistors of the first sub-deck structure to gate electrodes of the second vertical transistors of the second sub-deck structure;
- and
- at least a second deck structure comprising a second control logic level vertically overlying the first deck structure.
A device, comprising:
- a first deck structure comprising a first control logic level comprising complementary metal-oxide-semiconductor (CMOS) devices vertically neighboring at least one of a first access device level and a first memory element level, the CMOS devices comprising:
- a first sub-deck structure comprising an array of first vertical transistors;
- a second sub-deck structure vertically neighboring the first sub-deck structure and comprising an array of second vertical transistors;
- an output structure electrically coupled to at least some of the first vertical transistors of the array of first vertical transistors and at least some of the second vertical transistors of the array of second vertical transistors;
- and
- a second deck structure comprising a second control logic level comprising additional CMOS devices vertically neighboring the first deck structure.
Dependencies are inferred from the claim text.