High reliability polysilicon components

A method, comprising

• generating gate level passive component geometries of an integrated circuit design;
• generating isolation level geometries of the circuit design, including a subset of the isolation level geometries that correspond to the passive components;
• determining geometries of a well-implant block that correspond to the subset of isolation level geometries;
• and
• implementing a photomask that includes optical elements corresponding to the well-implant block geometries.

A method of forming an integrated circuit, comprising:

• forming a buried layer within an epitaxial layer having a top surface and a first conductivity type and located over a semiconductor substrate, the buried layer having a second opposite conductivity type;
• and
• forming one or more deep wells having the second conductivity type and extending from the top surface to the buried layer;
• and
• forming a lightly doped region having the first conductivity type, the lightly doped region surrounded by the buried layer and the one or more deep wells;
• forming a shallow well having the first conductivity type within the lightly doped region;
• and
• forming a dielectric isolation structure abutting the shallow well having the first conductivity type, the dielectric isolation structure touching the lightly doped region.

A method, comprising:

• forming a first well having a first conductivity type within an enclosed portion of a lightly doped epitaxial layer having the first conductivity type, the enclosed portion touching and being bounded laterally by deep wells having a second opposite conductivity type and further touching and being bounded vertically by a buried layer having the second conductivity type connecting the deep wells;
• forming a transistor formed in or over the first well and having a polysilicon gate electrode formed in a gate-layer;
• forming a dielectric isolation structure touching the enclosed portion of the lightly doped epitaxial layer;
• and
• forming a passive component formed in the gate-layer and located over the dielectric isolation structure.