Semiconductor devices having improved layout designs, and methods of designing and fabricating the same

A semiconductor device including a first cell region, comprising:

• an active pattern extending in a first direction, inside the first cell region;
• a gate electrode extending in a second direction intersecting the first direction, inside the first cell region;
• a source/drain contact connected to a source/drain region of the active pattern, on one side of the gate electrode;
• and
• a first wiring pattern extending in the first direction and connected to one of the gate electrode and the source/drain contact;
• wherein a part of the first wiring pattern protrudes from a boundary of the first cell region, and wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.

A semiconductor device which includes a first cell region and a second cell region adjacent to each other and arranged along a first direction, the semiconductor device comprising:

• a substrate;
• a first cell separation pattern which extends in a second direction intersecting the first direction to separate the first cell region and the second cell region, on the substrate;
• an active pattern extending in the first direction, on the substrate;
• a first gate electrode, which extends in the second direction and is spaced apart from the first cell separation pattern by one gate pitch, on the substrate in the first cell region;
• a first source/drain contact connected to a source/drain region of the active pattern of the first cell region, on one side of the first gate electrode;
• and
• a first wiring pattern, which extends in the first direction over the first cell region and the second cell region, and is connected to one of the first gate electrode and the first source/drain contact;
• and
• wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.

A layout design method for a semiconductor device, the method comprising:

• providing a first cell region;
• and
• providing a second cell region arranged adjacent to the first cell region along a first direction;
• wherein the first cell region includes:
• a gate electrode extending in a second direction intersecting the first direction;
• a source/drain contact connected to a source/drain region of the first cell region, on one side of the gate electrode;
• and
• a first wiring pattern which extends in the first direction over the first cell region and the second cell region, and is connected to one of the gate electrode and the source/drain contact.