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US 2022/0189934 A1Published application
Backside Interconnection Interface Die For Integrated Circuits Package
AssigneeGoogle Inc.
InventorsNamhoon Kim, Woon-Seong Kwon, Teckgyu Kang
Life of this patent
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Abstract
The technology relates to an integrated circuit (IC) package in which an interconnection interface chiplet and/or interconnection interface circuit are relocated, partitioned, and/or decoupled from a main or core IC die and/or high-bandwidth memory (HBM) components in an integrated component package.
Claims20
An integrated circuit (IC) package comprising:
- an interposer disposed on a first surface of a package substrate;
- a first IC logic die disposed on the interposer;
- and
- an interconnection interface chiplet disposed on a second surface of the package substrate opposite the first surface of the package substrate.
1 more element
An integrated circuit (IC) package comprising:
- an IC logic die disposed on a first surface of a package substrate;
- and
- an interconnection interface chiplet disposed on a second surface of the package substrate opposite to the first surface of the package substrate.
An integrated circuit (IC) package comprising:
- an IC logic die disposed on a first surface of a package substrate;
- and
- an interconnection interface chiplet disposed on a second surface of the package substrate vertically below the IC logic die.
Dependencies are inferred from the claim text.