Buffer Layer(s) on a Stacked Structure Having a Via

A method comprising:

• bonding a first substrate to a second substrate, the first substrate comprising a semiconductor substrate, electrical devices on the semiconductor substrate, and an interconnect structure, the interconnect structure and the electrical devices being at a first side of the semiconductor substrate, the interconnect structure being disposed between the semiconductor substrate and the second substrate after the bonding;
• forming a first stress buffer layer over a second side of the semiconductor substrate opposing the first side of the semiconductor substrate;
• forming a post-passivation interconnect (PPI) structure over the first stress buffer layer and electrically coupled to the interconnect structure;
• forming openings that extend through a first region of the PPI structure;
• forming a second stress buffer layer over the PPI structure and the first stress buffer layer, the second stress buffer layer extending into the openings and contacting the first stress buffer layer;
• and
• forming an external electrical connector over the second stress buffer layer and the first region of the interconnect structure.

A method comprising:

• bonding a first substrate to a second substrate, the first substrate comprising a first semiconductor substrate, electrical devices at a first side of the first semiconductor substrate, and a first interconnect structure at the first side of the first semiconductor substrate, the second substrate comprising a second semiconductor substrate and a second interconnect structure on the second semiconductor substrate, wherein after the bonding, the first interconnect structure and the second interconnect structure are disposed between the first semiconductor substrate and the second semiconductor substrate;
• forming a through via extending from a second side of the first semiconductor substrate opposite from the first side of the first semiconductor substrate, the through via extending through the first semiconductor substrate at least to the first interconnect structure;
• forming a first stress buffer layer over the through via and the second side of the first semiconductor substrate;
• forming a post-passivation interconnect (PPI) structure over the first stress buffer layer, the PPI structure extending through the first stress buffer layer to electrically couple to the through via, wherein the PPI structure is formed to have openings in a first region of the PPI structure;
• forming a second stress buffer layer over the PPI structure and the first stress buffer layer, wherein portions of the second stress buffer layer extend through the openings to contact the first stress buffer layer;
• and
• forming an external electrical connection structure over the first region of the PPI structure.