US 2022/0189924 A1Published application

Semiconductor package including stacked semiconductor chips

AssigneeSK hynix Inc.

InventorJin Kyoung PARK

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Abstract

A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer.

Claims23

Dependent claims

A semiconductor package comprising:

a base layer;
a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge of each of the plurality of semiconductor chips, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks;
a first inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first chip stack to each other;
a first stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first chip stack to the base layer;
a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the second chip stack to each other;
and
a second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the second chip stack to the base layer,
wherein the power-applied chip identification pads in the first chip stack are arranged so that the first inter-chip wire does not skip making contact with a power-applied chip identification pad of any one of the plurality of semiconductor chips included in the first chip stack, and
the power-applied chip identification pads in the second chip stack are arranged so that the second inter-chip wire does not skip making contact with a power-applied chip identification pad of any one of the plurality of semiconductor chips included in the second chip stack.

6 more elements

The semiconductor package according to claim wherein each of the first and second chip stacks includes first to fourth semiconductor chips,

the chip identification pads include first and second chip identification pads,
in the first chip stack, power is applied to the first and second chip identification pads of the first semiconductor chip, one of the first and second chip identification pads of the second semiconductor chip, and the other of the first and second chip identification pads of the third semiconductor chip, and
in the second chip stack, the power is applied to the first and second chip identification pads of the first semiconductor chip, one of the first and second chip identification pads of the second semiconductor chip, and the other of the first and second chip identification pads of the third semiconductor chip.

Dependencies are inferred from the claim text.