Stacked die circuit routing system and method
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn WUU, David JOHNSON
Life of this patent
Estimating the term…
Abstract
A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit.
Claims20
A system in package comprising:
- a first die comprising a first set of one or more metal layers of a first circuit;
- a second die stacked overlying the first die, wherein the second die comprises a second set of one or more metal layers of a second circuit, and wherein the second die has a same design as the first die, and wherein the second circuit corresponds to the first circuit;
- and
- a third die stacked overlying the second die, wherein the first die and the second die are configured to send a signal from the first die to the third die via either the first circuit or the second circuit but not both.
A method comprising:
- receiving a signal at a first interface of a first semiconductor die of a stacked semiconductor device;
- routing the signal to a third semiconductor die of the stacked semiconductor device via a second semiconductor die of the stacked semiconductor device, comprising sending the signal through a respective circuit of either the first semiconductor die or the second semiconductor die, but not both;
- and
- wherein the first semiconductor die has a same design as the second semiconductor die.
A non-transitory computer readable storage medium embodying a set of executable instructions, the set of executable instructions to manipulate a fabrication system to perform a portion of a process to fabricate at least part of a hardware integrated circuit, the hardware integrated circuit comprising:
- a first semiconductor die comprising a first set of one or more metal layers of a first circuit;
- a second semiconductor die stacked vertically over the first semiconductor die, wherein the second semiconductor die comprises a second set of one or more metal layers of a second circuit, and wherein the second semiconductor die has a same design as the first semiconductor die, and wherein the second circuit corresponds to the first circuit;
- and
- a third semiconductor die stacked vertically over the second semiconductor die, wherein the first semiconductor die and the second semiconductor die are configured to send a signal from the first semiconductor die to the third semiconductor die via either the first circuit or the second circuit but not both.
Dependencies are inferred from the claim text.