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US 2022/0189914 A1Published application
Semiconductor package including stacked semiconductor chips
AssigneeSK hynix Inc.
InventorJin Kyoung PARK
Life of this patent
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Abstract
A semiconductor package including: a base layer; and a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks.
Claims20
A semiconductor package comprising:
- a base layer;
- and
- a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads at one side edge of each of the first to fourth semiconductor chips, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first and second chip identification pads for identifying the first to fourth semiconductor chips in each of the first and second chip stacks,
- wherein power is applied to the stack identification pads of the first to fourth semiconductor chips of one of the first and second chip stacks,
- in the first chip stack, the power is applied to the first and second chip identification pads of the first semiconductor chip, one of the first and second chip identification pads of the second semiconductor chip, and the other of the first and second chip identification pads of the third semiconductor chip, and
- in the second chip stack, the power is applied to the first and second chip identification pads of the first semiconductor chip, one of the first and second chip identification pads of the second semiconductor chip, and the other of the first and second chip identification pads of the third semiconductor chip.
3 more elements
A semiconductor package comprising:
- a base layer;
- and
- a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including first to eighth semiconductor chips which are offset stacked to expose chip pads at one side edge of each of the first to eighth semiconductor chips, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack, and first to third chip identification pads for identifying the first to eighth semiconductor chips in each of the first and second chip stacks,
- wherein power is applied to the stack identification pads of the first to eighth semiconductor chips of one of the first and second chip stacks,
- in the first chip stack, the power is applied to the first to third chip identification pads of the first semiconductor chip, two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, where the selected two of the second semiconductor chip, the selected two of the third semiconductor chip, and the selected two of the fourth semiconductor chip are different from each other, and the selected one of the fifth semiconductor chip, the selected one of the sixth semiconductor chip, and the selected one of the seventh semiconductor chip are different from each other, and
- in the second chip stack, the power is applied to the first to third chip identification pads of the first semiconductor chip, two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, where the selected two of the second semiconductor chip, the selected two of the third semiconductor chip, and the selected two of the fourth semiconductor chip are different from each other, and the selected one of the fifth semiconductor chip, the selected one of the sixth semiconductor chip, and the selected one of the seventh semiconductor chip are different from each other.
3 more elements
Dependencies are inferred from the claim text.