Semiconductor package including stacked semiconductor chips
AssigneeSK hynix Inc.
InventorJong Hyun KIM
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AssigneeSK hynix Inc.
InventorJong Hyun KIM
Estimating the term…
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.
A semiconductor package comprising:
The semiconductor package according to claim wherein the chip pad portion further includes a passivation layer with an opening that exposes the chip pad, and
The semiconductor package according to claim wherein the redistribution pad extends in a direction opposite to an offset direction of the first to Nth semiconductor chips, and
A method for fabricating a semiconductor package, comprising:
The method according to Tim 21, wherein the chip pad portion further includes an insulating pattern that is interposed between the redistribution pad and the passivation layer.
Dependencies are inferred from the claim text.