Multi-side power delivery in stacked memory packaging

A method for constructing a packaged Integrated Circuit (IC) comprising:

• forming first level conductive posts on a carrier substrate;
• attaching a first side of a memory to the carrier substrate, the memory having a second side with conductive contacts for power inputs and data connections of the memory;
• encapsulating the first level conductive posts and the memory with first encapsulant that contacts the carrier substrate on a first side and has an exposed second side;
• placing a Redistribution Layer (RDL) on the exposed second side of the first encapsulant, such that a first side of the RDL is disposed proximate to and extends beyond the second side of the memory;
• forming second level conductive posts on a second side of the RDL;
• placing a processor on the second side of the RDL such that a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor;
• encapsulating the second level conductive posts and the processor with second encapsulant that contacts the second side of the RDL and has an exposed second side;
• and
• forming a fanout layer on the exposed second side of the second encapsulant such that:
• a first plurality of the second level conductive posts provide data communication links, via the RDL, between the processor and the conductive contacts for the data connections of the memory;
• a second plurality of the second level conductive posts are coupled, via the RDL, to the conductive contacts for the power inputs of the memory;
• and
• the first level conductive posts and a third plurality of the second level conductive posts form Through Mold Vias (TMVs) extending between the carrier substrate and the fanout layer.

A packaged Integrated Circuit (IC) comprising:

• a fanout layer including conductive lines and conductive vias;
• a processor having a first surface residing substantially adjacent a first surface of the fanout layer;
• a plurality of conductive posts extending from the fanout layer;
• a first encapsulant surrounding at least a portion of the processor and the plurality of conductive posts, the first encapsulant contacting the fanout layer on a first side and having an exposed second side;
• a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor and the exposed second side of the first encapsulant;
• a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor;
• a first plurality of conductive posts coupled between the fanout layer and the RDL through a portion of the first encapsulant disposed beneath the first portion of the memory proximate a first side of the processor, the first plurality of conductive posts providing data communication links between the processor and the memory;
• a second plurality of conductive posts coupled between the fanout layer and conductive features of the RDL through a portion of the first encapsulant that is proximate a second side of the processor, the conductive features of the RDL coupled to power inputs of the second portion of the memory;
• a first plurality of Through Mold Vias (TMVs) extending from the fanout layer through the first encapsulant;
• a second encapsulant surrounding at least a portion of the memory and the RDL;
• and
• a second plurality of TMVs extending from the first plurality of TMVs through the second encapsulant.