Fet construction with copper pillars or bump directly over the fet
AssigneeTexas Instruments Incorporated
InventorManoj Kumar Jain
Life of this patent
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Abstract
A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.
Claims21
A semiconductor device, comprising:
- a substrate, the substrate including a semiconductor material;
- a semiconductor component extending into the semiconductor material;
- an interconnect region over the semiconductor component;
- a top metal layer in the interconnect region;
- a protective dielectric layer on the top metal layer;
- a first top metal interconnect lead in the top metal layer;
- a second top metal interconnect lead in the top metal layer;
- top metal vias through the protective dielectric layer, the top metal vias contacting the first top metal interconnect lead;
- and
- a metal pillar electrically connected to the top metal vias;
- wherein:
- the metal pillar extends over a portion of the second top metal interconnect lead;
- the protective dielectric layer separates the metal pillar from the second top metal interconnect lead;
- and
- the semiconductor device is free of a direct electrical connection through the protective dielectric layer from the metal pillar to the second top metal interconnect lead.
A method of forming a semiconductor device, comprising:
- forming a semiconductor device extending into a semiconductor material of a device substrate;
- forming an interconnect region on the semiconductor device, the interconnect region including a top metal layer;
- forming a first top metal interconnect lead in the top metal layer and a second top metal interconnect lead in the top metal layer adjacent to the first top metal interconnect lead;
- forming a protective dielectric layer on the top metal layer;
- removing the protective dielectric layer in a top via openings in the protective dielectric layer to expose a portion of the first top metal interconnect lead;
- forming top metal vias in the top via openings contacting the first top metal interconnect lead;
- and
- forming a metal pillar on the top metal vias;
- wherein:
- the metal pillar extends over a portion of the second top metal interconnect lead;
- the protective dielectric layer separates the metal pillar from the second top metal interconnect lead;
- and
- the semiconductor device is free of a direct electrical connection through the protective dielectric layer from the metal pillar to the second top metal interconnect lead.
A semiconductor device, comprising:
- an interconnect region over a device substrate;
- a top metal layer in the interconnect region;
- a protective dielectric layer on the top metal layer;
- a first top metal interconnect lead in the top metal layer;
- a second top metal interconnect lead in the top metal layer;
- a via level including first top metal vias through the protective dielectric layer and second top metal vias through the protective dielectric layer, the first top metal vias contacting the first top metal interconnect lead and the second top metal vias contacting the second top metal interconnect lead;
- and
- a first metal pillar on the first top metal vias and a second metal pillar on the second top metal vias;
- wherein:
- the first metal pillar extends over a portion of the second top metal interconnect lead and the second metal pillar extends over a portion of the first top metal interconnect lead;
- the protective dielectric layer separates the first metal pillar from the second top metal interconnect lead and the second metal pillar from the first top metal interconnect lead;
- and
- the via level includes no vias between the first metal pillar and the second top metal interconnect lead and no vias between the second metal pillar and the first top metal interconnect.
Dependencies are inferred from the claim text.