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US 2022/0189888 A1Published application
Semiconductor structure
AssigneeUnited Microelectronics Corp.
InventorsChien-Ming Lai, Hui-Ling Chen, Zhi-Rui Sheng
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Abstract
A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.
Claims13
A semiconductor structure, comprising:
- a first semiconductor wafer, comprising a first semiconductor substrate and a first inductance layer, wherein the first inductance layer is disposed on the first semiconductor substrate, one side of the first inductance layer away from the first semiconductor substrate has a first bonding surface, the first inductance layer comprises at least one first metal trace, at least one first interconnect structure and a first insulating layer, the first insulating layer covers the at least one first metal trace, and the at least one first interconnect structure is embedded in the first insulating layer and electrically connected to the at least one first metal trace;
- and
- a second semiconductor wafer, comprising a second semiconductor substrate and a second inductance layer, wherein the second inductance layer is disposed on the second semiconductor substrate, one side of the second inductance layer away from the second semiconductor substrate has a second bonding surface, the second inductance layer comprises at least one second metal trace, at least one second interconnect structure and a second insulating layer, the second insulating layer covers the at least one second metal trace, and the at least one second interconnect structure is embedded in the second insulating layer and electrically connected to the at least one second metal trace,
- wherein, the first semiconductor wafer and the second semiconductor wafer are coupled to each other, the first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer, the first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond, and the at least one first interconnect structure on the first bonding surface and the at least one second interconnect structure on the second bonding surface form a second bond.
1 more element
A semiconductor structure, comprising:
- a first semiconductor wafer, comprising a first semiconductor substrate and a first inductance layer, wherein the first inductance layer is disposed on the first semiconductor substrate, one side of the first inductance layer away from the first semiconductor substrate has a first bonding surface, and the first inductance layer comprises a start metal trace, a plurality of first metal traces, a plurality of first interconnect structures and a first insulating layer, wherein
- the start metal trace and the first metal traces are arranged side by side, the start metal trace has an input terminal and a first terminal, and each of the first metal traces has a first connection terminal and a second connection terminal,
- the first insulating layer covers the start metal trace and the first metal traces,
- the first interconnect structures are embedded in the first insulating layer, and the first terminal, each of the first connection terminals, and each of the second connection terminals are each electrically connected to one of the first interconnect structures;
- and
- a second semiconductor wafer, comprising a second semiconductor substrate and a second inductance layer, wherein the second inductance layer is disposed on the second semiconductor substrate, one side of the second inductance layer away from the second semiconductor substrate has a second bonding surface, and the second inductance layer comprises a plurality of second metal traces, a plurality of second interconnect structures and a second insulating layer, wherein
- the second metal traces are arranged side by side, and each of the second metal traces has a third connection terminal and a fourth connection terminal,
- the second insulating layer covers the second metal traces,
- the second interconnect structures are embedded in the second insulating layer, and the third connection terminals and the fourth connection terminals are each electrically connected to one of the second interconnect structures,
- wherein, the first semiconductor wafer and the second semiconductor wafer are coupled to each other, the first bonding surface of the first inductance layer is bonded to the second bonding surface of the second inductance layer, the first insulating layer on the first bonding surface and the second insulating layer on the second bonding surface form a first bond, the first interconnect structures on the first bonding surface and the second interconnect structures on the second bonding surface respectively form a second bond, and the start metal trace, the first metal traces, the first interconnect structures, the second metal traces and the second interconnect structures form a multi-circle continuous and non-intersecting path and constitute an inductance element.
7 more elements
Dependencies are inferred from the claim text.