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US 2022/0189879 A1Published application
Multirow semiconductor chip connections
AssigneeAdvanced Micro Devices, Inc.
InventorsRAHUL AGARWAL, MILIND S. BHAGAVAT
Life of this patent
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Abstract
A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.
Claims20
A method of manufacturing a semiconductor device, comprising:
- mounting an interconnect chip to a redistribution layer structure;
- and
- mounting a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip to the redistribution layer structure, the second semiconductor chip being interposed between the first semiconductor chip and the third semiconductor chip, and the interconnect chip communicatively coupling the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip to one another.
An interconnect chip, comprising:
- an interconnect layer having a first portion comprising a first plurality of interconnect points configured to electrically couple to a physical device region of a first semiconductor chip, a mid-portion comprising a second plurality of interconnect points configured to electrically couple to a physical device region of a second semiconductor chip, and a second portion comprising a third plurality of interconnect points configured to electrically couple to a physical device region of a third semiconductor chip, wherein the mid portion is interposed between the first portion and the second portion;
- and
- a plurality of interconnect paths, each interconnect path comprising a repeater and communicatively coupling an interconnect point of the first plurality of interconnect points to an interconnect point of the third plurality of interconnect points.
A semiconductor device, comprising:
- a redistribution layer having a plurality of conductive paths and a plurality of interconnect paths;
- at least three semiconductor chips mounted to the redistribution layer with at least one semiconductor chip interposed between two other semiconductor chips;
- and
- an interconnect chip mounted to the redistribution layer, the interconnect chip communicatively coupling the at least three semiconductor chips to one another.
1 more element
Dependencies are inferred from the claim text.