Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate;
• an active fin that protrudes from the substrate;
• a gate pattern that runs across the active fin, the gate pattern including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked;
• a source/drain pattern in the substrate on a side of the gate pattern;
• a contact pad on the source/drain pattern, the contact pad having a top surface lower than a top surface of the gate electrode;
• a source/drain contact on the contact pad;
• a gate spacer that includes a first segment between the gate pattern and the contact pad, a second segment between the gate pattern and the source/drain contact, and a third segment on the second segment, the third segment having a width less than a width of the second segment;
• a first dielectric spacer and a second dielectric spacer between the second segment and the source/drain contact;
• and
• a third dielectric spacer and a buried dielectric pattern between the third segment and the source/drain contact,
• wherein a width of the buried dielectric pattern is greater than a width of the first dielectric spacer, greater than a width of the second dielectric spacer, and greater than a width of the third dielectric spacer.

A semiconductor device, comprising:

• a substrate;
• a gate pattern on the substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked, the gate pattern having a first sidewall and a second sidewall that are opposite to each other;
• a source/drain pattern in the substrate adjacent to the first sidewall of the gate pattern;
• a contact pad on the source/drain pattern, the contact pad having a top surface lower than a top surface of the gate electrode;
• a source/drain contact on the contact pad;
• a first gate spacer that covers the first sidewall of the gate pattern;
• and
• a second gate spacer that covers the second sidewall of the gate pattern,
• wherein:
• the first gate spacer includes a first segment between the gate pattern and the contact pad, a second segment between the gate pattern and the source/drain contact, and a third segment on the second segment, the third segment having a width less than a width of the second segment, and
• the width of the third segment is less than a width of the second gate spacer.