Semiconductor device packages including multiple lead frames and related methods

A semiconductor device package, comprising:

• a first semiconductor die comprising a first major surface affixed and electrically connected to a first lead frame;
• a second semiconductor die comprising a second major surface affixed and electrically connected to a second lead frame, the second semiconductor die comprising a third major surface affixed to a fourth major surface of the first semiconductor die, such that the first lead frame is located on a side of the first semiconductor die distal the second semiconductor die and the second lead frame is located on a side of the second semiconductor die distal the first semiconductor die;
• and
• a molding material encapsulating the first semiconductor die, the second semiconductor die, and at least portions of the first lead frame and the second lead frame.

A method of concurrently making semiconductor device packages, comprising:

• affixing a first major surface of each of a plurality of semiconductor dice, and electrically connecting each semiconductor die, to respective first die-attach locations of a first lead frame;
• affixing a second major surface of each semiconductor die, and electrically connecting each semiconductor die, to respective second die-attach locations of a second lead frame, the second lead frame located on a side of each semiconductor die opposite the first lead frame;
• and
• encapsulating the semiconductor dice and at least portions of the first lead frame and the second lead frame in a molding material.

A method of concurrently making semiconductor device packages, comprising:

• affixing a first major surface of each of a plurality of first semiconductor dice, and electrically connecting each first semiconductor die, to respective first die-attach locations of a first lead frame;
• affixing a second major surface of each of a plurality of second semiconductor dice, and electrically connecting each second semiconductor die, to respective second die-attach locations of a second lead frame;
• securing each first semiconductor die to a corresponding second semiconductor die, the first lead frame located on a side of each first semiconductor die distal of the corresponding second semiconductor die, the second lead frame located on a side of each second semiconductor die distal of the first semiconductor die;
• and
• encapsulating the first semiconductor dice, the second semiconductor dice, and at least portions of the first lead frame and the second lead frame in a molding material.