Interposer and semiconductor package including the same

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip on the package substrate;
• a first conductive connector on the package substrate and laterally spaced apart from the semiconductor chip;
• an interposer substrate on the semiconductor chip, the interposer substrate including a first portion overlapping the semiconductor chip in a first direction perpendicular to an upper surface of the package substrate, a second portion connected to the first conductive connector, and a plurality of upper conductive pads at an upper surface of the first portion;
• and
• a plurality of spacers between a lower surface of the first portion of the interposer substrate and the semiconductor chip, and positioned so as not to overlap the plurality of upper conductive pads in a plan view.

An interposer for a semiconductor package, the interposer comprising:

• a base insulating layer;
• a plurality of upper conductive pads on an upper surface of the base insulating layer;
• an upper protective insulating layer covering the upper surface of the base insulating layer and including openings exposing the plurality of upper conductive pads;
• a plurality of lower conductive pads on a lower surface of the base insulating layer;
• a lower protective insulating layer covering the lower surface of the base insulating layer and including openings exposing the plurality of lower conductive pads;
• and
• a plurality of spacers on the lower protective insulating layer and positioned so as not to overlap the plurality of upper conductive pads in a plan view,
• wherein the plurality of upper conductive pads include four upper conductive pads arranged in a rectangular shape on the upper surface of the base insulating layer, and
• at least one of the plurality of spacers is between the four upper conductive pads in a plan view.