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US 2022/0189834 A1Published application
Method for testing semiconductor elements
AssigneeUpper Elec. Co., Ltd.
InventorShih Hung Lin
Life of this patent
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Abstract
Disclosed is a method for testing a semiconductor element. The method comprises forming at least one redistribution layer on a chip, utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip, and removing the at least one redistribution layer from the chip, wherein the length of each semiconductor element is between 2-150 μm and the width of each semiconductor element is between 2-150 μm.
Claims18
A method for testing a semiconductor element, comprising:
- (i) forming at least one redistribution layer on a chip;
- (ii) utilizing the at least one redistribution layer to test an array of semiconductor elements on the chip;
- and
- (iii) removing the at least one redistribution layer from the chip;
- wherein the length of each semiconductor element is between 2-150 μm and the width of each semiconductor element is between 2-150 μm.
2 more elements
Dependencies are inferred from the claim text.