Method for manufacturing logic device isolation in embedded storage process

A method for manufacturing logic device isolation in an embedded storage process, comprising the following steps:

• step 1. generating a floating gate oxide layer on a silicon substrate, generating a floating gate polysilicon layer on the floating gate oxide layer, and depositing pad silicon nitride on the floating gate polysilicon layer;
• step 2. performing shallow trench isolation lithography;
• step 3. performing vertical dry etching to remove the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retain the floating gate oxide layer;
• step 4. depositing acid etching silicon nitride;
• step 5. performing vertical dry etching to remove the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation;
• step 6. performing lateral SiN pull-back of the shallow trench isolation to remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation;
• step 7. performing silicon oxide filling of the shallow trench isolation;
• and
• step 8. performing chemical mechanical polishing to form logic device isolation.