Memory controller, memory device, and storage device

A storage device comprising:

• at least one memory device;
• and
• a memory controller configured to store a table, in which a static offset voltage for a read voltage is written, and a machine learning model determining a dynamic offset voltage for a read voltage, wherein the memory controller is connected to the memory device by:
• control pins providing at least one of a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a read enable (RE) signal, and a DQS signal, and
• data pins transmitting and receiving a data signal to and from the memory device, wherein:
• when an error in first read data, output by the memory device performing a first read operation, is not corrected, the memory controller controls the memory device to perform a second read operation including an on-chip valley search operation, and
• when an error in a second read voltage, output by the memory device performing a second read operation, is not corrected, the memory controller transmits to the machine learning model a corrected read voltage reflecting a dynamic offset voltage obtained by inputting at least a portion of detection information generated by the on-chip valley search operation.

A memory device comprising:

• an input/output interface including a plurality of control pins, receiving control signals from a memory controller, and a plurality of data pins, transmitting and receiving a data signal to and from the memory controller, and configured to receive at least one of a first read command and a second read command from the memory controller;
• a memory cell array having a plurality of memory cells;
• and
• a logic circuit configured to output read data, obtained from selected memory cells among the plurality of memory cells, to the memory controller in response to the first read command and the second read command, wherein:
• the logic circuit outputs cell count information, indicating a threshold voltage distribution of a plurality of states that the memory cells have, and a detection case, determined based on the cell count information, to the memory controller when receiving the second read command, and
• when the first read command for the selected memory cells is re-received from the memory controller after the cell count information is output, a read operation is performed using a read voltage included in the re-received first read command and the read data is output to the memory controller.