Distributed compaction of logical states to reduce program time

A method comprising:

• causing memory cells of a memory array to be programmed with an initial voltage distribution representing multiple logical states;
• causing, at an interval of the multiple logical states, the memory cells to be programmed with a first subsequent voltage distribution representing a first subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the first subset of the multiple logical states is compacted above a first program verify voltage level;
• causing a first program verify operation of the first subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the first subsequent voltage distribution;
• causing, at the interval, the memory cells to be programmed with a second subsequent voltage distribution representing a second subset of the multiple logical states at a higher voltage than that of the first subsequent voltage distribution, wherein the second subset of the multiple logical states is compacted above a second program verify voltage level that is greater than the first program verify voltage level;
• and
• causing a second program verify operation of the second subsequent voltage distribution to be performed to verify one or more voltage levels of the second subsequent voltage distribution.

A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

• causing memory cells of a memory array to be programmed with an initial voltage distribution representing multiple logical states;
• causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution;
• and
• causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.