Architecture and method for nand memory operation

A method for reading a memory device including a first memory cell string and a second memory cell string, the first memory cell string including a bottom-select-gate (BSG) transistor, memory cells, and a top-select-gate (TSG) transistor that are connected in series, the second memory cells string including a BSG transistor, memory cells, and a TSG transistor that are connected in series, the method comprising:

• applying, in a pre-verify stage, a first verify voltage on a gate terminal of a selected memory cell of the first memory cell string, the selected memory cell being programmed and arranged between a first adjacent memory cell and a second adjacent memory cell;
• applying, in the pre-verify stage, a first bias voltage on a gate terminal of at least one memory cell of the first memory cell string that is positioned between the second adjacent memory cell of the selected memory cell and the BSG transistor of the first memory cell string;
• applying, in a verify stage, a second verify voltage on the gate terminal of the selected memory cell of the first memory cell string;
• and
• applying, in the verify stage, a second bias voltage on the gate terminal of the at least one memory cell of the first memory cell string that is positioned between the second adjacent memory cell of the selected memory cell and the BSG transistor of the first memory cell string, wherein the second bias voltage is smaller than the first bias voltage.

An apparatus for reading a memory device including a first memory cell string and a second memory cell string, the first memory cell string including a bottom-select-gate (BSG) transistor, memory cells, and a top-select-gate (TSG) transistor that are connected in series, the second memory cells string including a BSG transistor, memory cells, and a TSG transistor that are connected in series, the apparatus comprising:

• processing circuitry configured to:
• apply, in a pre-verify stage, a first verify voltage on a gate terminal of a selected memory cell of the first memory cell string, the selected memory cell being programmed and arranged between a first adjacent memory cell and a second adjacent memory cell;
• apply, in the pre-verify stage, a first bias voltage on a gate terminal of at least one memory cell of the first memory cell string that is not programmed;
• apply, in a verify stage, a second verify voltage on the gate terminal of the selected memory cell of the first memory cell string;
• and
• apply, in the verify stage, a second bias voltage on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, wherein the second bias voltage is smaller than the first bias voltage.