Page buffer circuit with bit line select transistor

A memory device, comprising:

• a memory array including a plurality of memory strings, the memory strings being divided into a first memory string group and a second memory string group;
• a bitline including a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group;
• and
• a buffer,
• wherein the buffer is disposed closer to the first bitline segment than to the first memory string group and is connected to the first bitline segment through a first conduction path, and the buffer is disposed closer to the second bitline segment than to the second memory string group and is connected to the second bitline segment through a second conduction path.

A memory device, comprising:

• a first memory plane that includes a plurality of first memory arrays;
• first bitlines coupled to the first memory arrays of the first memory plane, respectively;
• a second memory plane that includes a plurality of second memory arrays;
• second bitlines coupled to the second memory arrays of the second memory plane, respectively;
• and
• page buffers each coupled to a corresponding one of the first bitlines and a corresponding one of the second bitlines.