Methods of forming transistors having raised extension regions

A method of forming a transistor, comprising:

• forming a dielectric overlying a semiconductor having a first conductivity type;
• forming a conductor overlying the dielectric;
• patterning the conductor and dielectric to define a gate stack of the transistor;
• forming a first extension region base in the semiconductor, wherein the first extension region base has a second conductivity type different than the first conductivity type, wherein the first extension region base extends beneath the gate stack in a first direction from a first edge of the gate stack, and wherein the first extension region base further extends away from the first edge of the gate stack in a second direction opposite the first direction;
• forming a second extension region base in the semiconductor, wherein the second extension region base has the second conductivity type, wherein the second extension region base extends beneath the gate stack in the second direction from a second edge of the gate stack opposite the first edge of the gate stack, and wherein the second extension region base further extends away from the second edge of the first gate stack in the first direction;
• forming a first extension region riser overlying the first extension region base, wherein the first extension region riser has the second conductivity type;
• forming a second extension region riser overlying the second extension region base, wherein the second extension region riser has the second conductivity type;
• forming a first source/drain region in the first extension region riser, wherein the first source/drain region has the second conductivity type and has a conductivity level greater than a conductivity level of the first extension region riser;
• and
• forming a second source/drain region in the second extension region riser, wherein the second source/drain region has the second conductivity type and has a conductivity level greater than a conductivity level of the second extension region riser.

A method of forming a pair of transistors, comprising:

• forming a first isolation region and a second isolation region in a semiconductor having a first conductivity type;
• forming a dielectric overlying the semiconductor, the first isolation region, and the second isolation region;
• forming a conductor overlying the dielectric;
• patterning the conductor and dielectric to define a first gate stack for a first transistor of the pair of transistors and to define a second gate stack for a second transistor of the pair of transistors, wherein the first gate stack and the second gate stack are overlying a portion of the semiconductor between the first isolation region and the second isolation region;
• forming a first extension region base in the semiconductor, wherein the first extension region base has a second conductivity type different than the first conductivity type, wherein the first extension region base extends beneath the first gate stack in a first direction from a first edge of the first gate stack, wherein the first extension region base further extends to a first edge of the second gate stack in a second direction from the first edge of the first gate stack opposite the first direction, and wherein the first extension region base further extends beneath the second gate stack in the second direction from the first edge of the second gate stack;
• forming a second extension region base in the semiconductor, wherein the second extension region base has the second conductivity type, wherein the second extension region base extends beneath the first gate stack in the second direction from a second edge of the first gate stack opposite the first edge of the first gate stack, and wherein the second extension region base further extends to the first isolation region in the first direction from the second edge of the first gate stack;
• forming a third extension region base in the semiconductor, wherein the third extension region base has the second conductivity type, wherein the third extension region base extends beneath the second gate stack in the first direction from a second edge of the second gate stack opposite the first edge of the second gate stack, and wherein the third extension region base further extends to the second isolation region in the second direction from the second edge of the second gate stack;
• forming a first extension region riser overlying the first extension region base, the first extension region riser having the second conductivity type;
• forming a second extension region riser overlying the second extension region base, the second extension region riser having the second conductivity type;
• forming a third extension region riser overlying the third extension region base, the third extension region riser having the second conductivity type;
• forming a first source/drain region in the first extension region riser, the first source/drain region having the second conductivity type and having a conductivity level greater than a conductivity level of the first extension region riser;
• forming a second source/drain region in the second extension region riser, the second source/drain region having the second conductivity type and having a conductivity level greater than a conductivity level of the second extension region riser;
• and
• forming a third source/drain region in the third extension region riser, the third source/drain region having the second conductivity type and having a conductivity level greater than a conductivity level of the third extension region riser.