Apparatus and methods including source gates

A memory device, comprising:

• multiple vertical strings of memory cells, each string of memory cells comprising multiple memory cells associated with a respective semiconductor channel material, wherein the multiple vertical strings of memory cells each include first and second select transistors which each partially control conduction between a common source and the semiconductor channel material, wherein each of the first and second select transistors in the respective vertical strings of memory cells include respective control gates;
• wherein the control gates of the first select transistors of the multiple memory cell strings are coupled together to be controlled in common;
• and
• wherein the control gates of the second select transistors of a first portion of the multiple strings are coupled together to be controlled together, but controlled separately from the control gates of the second select transistors of a second portion of the multiple strings.

A memory device, comprising:

• a block of multiple vertical strings of memory cells, each string of memory cells comprising multiple memory cells associated with a respective semiconductor channel material, wherein the multiple strings of memory cells each include a source gate transistor (SG) and a source gate select (SGS) transistor, which each partially control conduction between a source and the semiconductor channel material of the string;
• wherein gates of the source gate (SG) transistors of the multiple memory cell strings are coupled to an SG select line to be controlled in common;
• and
• wherein gates of the source gate select (SGS) transistors of a first portion of the multiple strings are coupled to a first SGS select line to be controlled together, and gates of the source gate select (SGS) transistors of a second portion of the multiple strings are coupled to a second SGS select line to be controlled together.