Techniques for programming a memory cell
AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
Life of this patent
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Abstract
Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
Claims20
A method, comprising:
- reducing, for a duration, a threshold voltage of a memory cell during a write operation by applying a first pulse to the memory cell having a first polarity, the memory cell comprising a first logic value;
- applying, during the duration, a second pulse to the memory cell during the write operation, the second pulse having a second polarity different than the first polarity;
- and
- storing a second logic value in the memory cell after applying the second pulse.
An apparatus, comprising:
- a controller associated with a memory system that comprises non-volatile memory, wherein the controller is configured to cause the apparatus to:
- reduce, for a duration, a threshold voltage of a memory cell during a write operation by applying a first pulse to the memory cell having a first polarity, the memory cell comprising a first logic value;
- apply, during the duration, a second pulse to the memory cell during the write operation, the second pulse having a second polarity different than the first polarity;
- and
- store a second logic value in the memory cell after applying the second pulse.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
- reduce, for a duration, a threshold voltage of a memory cell during a write operation by applying a first pulse to the memory cell having a first polarity, the memory cell comprising a first logic value;
- apply, during the duration, a second pulse to the memory cell during the write operation, the second pulse having a second polarity different than the first polarity;
- and
- store a second logic value in the memory cell after applying the second pulse.
Dependencies are inferred from the claim text.