Mixed conducting volatile memory element for accelerated writing of nonvolatile memristive device
AssigneeInternational Business Machines Corporation
InventorsKevin W. Brew, Wei Wang, Injo Ok, Lan Yu, Youngseok Kim
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Abstract
An embodiment in the application may include an analog memory structure, and methods of writing to such a structure, including a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.
Claims25
A memory structure comprising:
- a volatile memory element in series with a non-volatile memory element.
A memory structure comprising:
- a volatile memory layer in series with a memristive element.
A method of writing to a memory structure comprising:
- applying a first pulse to an analog memory structure, wherein the analog memory structure comprises a volatile memory element and a non-volatile memristive element in series;
- and
- applying a second pulse to the analog memory structure, wherein a time between the first pulse and the second pulse is less than a relaxation rate of the volatile memory element.
A method of writing to a memory structure comprising:
- applying a first pulse to an analog memory structure, wherein the analog memory structure comprises a volatile memory element and a non-volatile memristive element in series;
- applying a second pulse to the analog memory structure, and wherein a first time between the first pulse and the second pulse is less than a relaxation rate of the volatile memory element;
- and
- applying a third negative pulse to the analog memory structure, wherein a second time between the second pulse and the third negative pulse is less than the relaxation rate of the volatile memory element and more than the first time.
A method of writing to an analog memory structure comprising:
- applying a first pulse to an analog memory structure, wherein the analog memory structure comprises a volatile memory element and a non-volatile memristive element in series;
- applying a second pulse to the analog memory structure, and wherein a first time between the first pulse and the second pulse is less than a relaxation rate of the volatile memory element;
- and
- applying a third pulse to the analog memory structure, wherein a second time between the second pulse and the third pulse is less than the relaxation rate of the volatile memory element and more than the first time.
Dependencies are inferred from the claim text.