Decoding for a memory device

An apparatus, comprising:

• a substrate extending in a first direction and a second direction;
• a memory array comprising:
• a memory cell;
• a digit line coupled with the memory cell;
• a word line coupled with the memory cell and extending in the second direction parallel with the substrate;
• and
• a decoder coupled with the digit line and comprising a first stage and a second stage, the first stage of the decoder positioned in a first layer comprising one or more logic circuits associated with operating the memory array, the second stage of the decoder positioned in a second layer between the first layer and the memory array, the second stage of the decoder comprising:
• a p-type transistor coupled with a source node and the digit line, the source node configured to bias the digit line to a first voltage based at least in part on operation of the p-type transistor, the p-type transistor comprising a first doped material;
• and
• an n-type transistor coupled with a ground node and the digit line, the ground node configured to bias the digit line to a ground voltage based at least in part on operation of the n-type transistor, the n-type transistor comprising a second doped material.

A method, comprising:

• biasing, using a first stage of a decoder, a source node to a first voltage as part of an access operation on a memory array;
• coupling, using a second stage of the decoder, the source node or a ground node with an access line of the memory array;
• biasing a memory cell of the memory array coupled with the access line based at least in part on coupling the source node or the ground node with the access line;
• and
• performing the access operation on the memory cell based at least in part on biasing the memory cell.

An apparatus, comprising:

• a memory array;
• a decoder comprising a first stage and a second stage and coupled with the memory array;
• and
• a controller coupled with the decoder and the memory array, the controller operable to cause the apparatus to:
• bias, using the first stage of the decoder, a source node to a first voltage as part of an access operation on the memory array;
• couple, using the second stage of the decoder, the source node or a ground node with an access line of the memory array;
• bias a memory cell of the memory array coupled with the access line based at least in part on coupling the source node or the ground node with the access line;
• and
• perform the access operation on the memory cell based at least in part on biasing the memory cell.