Decoding for a memory device

An apparatus, comprising:

• a substrate extending in a first direction and a second direction;
• a memory array comprising:
• a memory cell;
• a pillar configured as a digit line and coupled with the memory cell, the pillar extending in a third direction different than the first direction and the second direction;
• a word line coupled with the memory cell in the second direction parallel with the substrate;
• a decoder coupled with the pillar and comprising a first stage and a second stage, the first stage of the decoder positioned in a first layer comprising one or more logic circuits associated with operating the memory array, the second stage of the decoder positioned in a second layer between the first layer and the memory array, the second stage of the decoder comprising:
• a first vertical transistor coupled with a source node and the pillar, the source node configured to bias the pillar to a first voltage based at least in part on operation of the first vertical transistor, the first vertical transistor comprising a first doped material that extends in the third direction;
• and
• a second vertical transistor coupled with a ground node and the pillar, the ground node configured to bias the pillar to ground based at least in part on operation of the second vertical transistor, the second vertical transistor comprising a second doped material that extends in the third direction.

A method, comprising:

• forming a layer comprising a first stage of a decoder associated with an array of memory cells, the layer and the array of memory cells extending in a first direction and a second direction;
• depositing a first conductive line and a second conductive line extending in the first direction based at least in part on forming the layer;
• depositing a first dielectric material over the first conductive line and the second conductive line;
• forming a first opening in the first dielectric material that exposes the first conductive line and a second opening in the first dielectric material that exposes the second conductive line by etching a portion of the first dielectric material;
• depositing, into the first opening, a first material to form a first junction in contact with the first conductive line;
• depositing, into the second opening, a second material to form a second junction in contact with the second conductive line;
• depositing a first doped material to form a first n-type transistor in contact with the first junction;
• depositing a second doped material to form a second n-type transistor in contact with the second junction, wherein the first n-type transistor and the second n-type transistor comprise a portion of a second stage of the decoder;
• and
• forming the array of memory cells based at least in part on depositing the first doped material and the second doped material.

A method, comprising:

• biasing, using a first stage of a decoder, a source node to a first voltage as part of an access operation on a memory array;
• coupling, using a second stage of the decoder, the source node or a ground node with an access line of the memory array, wherein coupling the source node or the ground node with the access line comprises:
• biasing a first gate of a first n-type transistor to a positive voltage and a second gate of a second n-type transistor to a negative voltage;
• activating the first n-type transistor based at least in part on biasing the first gate of the first n-type transistor to the positive voltage, wherein the source node is coupled with the access line based at least in part on activating the first n-type transistor;
• and
• deactivating the second n-type transistor based at least in part on biasing the second gate of the second n-type transistor to the negative voltage, wherein the ground node is isolated from the access line based at least in part on deactivating the second n-type transistor;
• biasing a memory cell of the memory array coupled with the access line based at least in part on coupling the source node or the ground node with the access line;
• and
• performing the access operation on the memory cell based at least in part on biasing the memory cell.

An apparatus, comprising:

• a memory array;
• a decoder comprising a first stage and a second stage and coupled with the memory array;
• and
• a controller coupled with the decoder and the memory array, the controller operable to cause the apparatus to:
• bias, using the first stage of the decoder, a source node to a first voltage as part of an access operation on the memory array;
• couple, using the second stage of the decoder, the source node or a ground node with an access line of the memory array, wherein the controller being operable to cause the apparatus to couple the source node or the ground node with the access line comprises the controller being operable to cause the apparatus to:
• bias a first gate of a first n-type transistor to a positive voltage and a second gate of a second n-type transistor to a negative voltage;
• activate the first n-type transistor based at least in part on biasing the first gate of the first n-type transistor to the positive voltage, wherein the source node is coupled with the access line based at least in part on activating the first n-type transistor;
• and
• deactivate the second n-type transistor based at least in part on biasing the second gate of the second n-type transistor to the negative voltage, wherein the ground node is isolated from the access line based at least in part on deactivating the second n-type transistor;
• bias a memory cell of the memory array coupled with the access line based at least in part on coupling the source node or the ground node with the access line;
• and
• perform the access operation on the memory cell based at least in part on biasing the memory cell.

The apparatus of claim 34, wherein the controller being operable to:

• bias the first gate of the first n-type transistor to a second voltage and the second gate of the second n-type transistor to a third voltage;
• activate the second n-type transistor based at least in part on biasing the second gate of the second n-type transistor to the third voltage, wherein the ground node is coupled with the access line based at least in part on activating the second n-type transistor;
• and
• deactivate the first n-type transistor based at least in part on biasing the first gate of the first n-type transistor to the second voltage, wherein the source node is isolated from the access line based at least in part on deactivating the first n-type transistor.