US 2022/0189543 A1 · ENHANCED STATE DUAL MEMORY CELL

Abstract

A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Claims25

Dependent claims

A circuit comprising:

a memory array, the memory a comprises
a plurality of bit lines;
a plurality of word lines;
a plurality of select lines, the plurality of bit lines and the plurality of select lines intersect the plurality of word lines;
and
a plurality of memory cells each comprising
a first transistor,
a second transistor,
a first memory element, and
a second memory element, the first and second memory elements are connected to the plurality of word lines by way of the first and second transistors, the first and second memory elements are connected to the plurality of bit lines and the plurality of select lines.

7 more elements

Dependencies are inferred from the claim text.

Enhanced state dual memory cell

Life of this patent

Enhanced state dual memory cell

Life of this patent

Abstract

Claims25