Circuit and method of writing to a bit cell

A memory circuit comprising:

• first and second bit lines;
• a memory domain comprising:
• a memory domain power node having a memory domain power voltage level;
• a memory domain reference node having a memory domain reference voltage level;
• a bit cell coupled to each of the first and second bit lines and the memory domain power and reference nodes;
• a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between the first bit line and the memory domain power node, thereby configured to selectively drive the bit cell to the memory domain power voltage level;
• a second PMOS transistor coupled between the second bit line and the memory domain power node, thereby configured to selectively drive the bit cell to the memory domain power voltage level;
• and
• first and second inverter pairs;
• and
• a second domain comprising:
• a second domain power node having a second domain power voltage level less than the memory domain power voltage level;
• a second domain reference node having a second domain reference voltage level;
• a first n-type metal-oxide-semiconductor (NMOS) transistor coupled between the first bit line and the second domain reference node, thereby configured to selectively drive the bit cell to the second domain reference voltage level;
• a second NMOS transistor coupled between the second bit line and the second domain reference node, thereby configured to selectively drive the bit cell to the second domain reference voltage level;
• first and second NAND gates;
• a first NOR gate coupled between an output terminal of the first NAND gate and a gate of the first NMOS transistor;
• and
• a second NOR gate coupled between an output terminal of the second NAND gate and a gate of the second NMOS transistor,
• wherein
• the first inverter pair is coupled between the output terminal of the first NAND gate and a gate of the second PMOS transistor, and
• the second inverter pair is coupled between the output terminal of the second NAND gate and a gate of the first PMOS transistor.

A method of performing a write operation, the method comprising:

• coupling a bit cell of a memory domain to first and second bit lines;
• using first and second logic gates, generating first complementary signals in a second domain having a power voltage level less than a power voltage level of the memory domain;
• in response to the first complementary signals and a write decode signal, using a first NOR gate in the second domain to drive the first bit line to a reference voltage level;
• using first and second converter circuits, converting the first complementary signals to second complementary signals in the memory domain;
• and
• in response to the second complementary signals, using a first pass gate in the memory domain to drive the second bit line to the power voltage level of the memory domain.