Control circuit of memory device

A device, comprising:

• a write driver, configured to provide a bit line voltage and a complement bit line voltage to a memory array;
• a write assist circuit, coupled with the write driver, the write assist circuit is configured to pull down one voltage level on the bit line or the complement bit line to a transient negative voltage level in response to a negative bit line trigger signal;
• and
• a timing control circuit, coupled with the write assist circuit, wherein the timing control circuit comprises a tracking word line relative to a first delay on a word line in the memory array and a tracking bit line relative to a second delay on a bit line in the memory array, the timing control circuit is configured to generate the negative bit line trigger signal in response to a clock pulse signal with reference to the first delay and the second delay.

A method, comprising:

• transmitting a clock pulse signal through a tracking word line;
• discharging a voltage level on a first node in response to the clock pulse signal, the first node being coupled to a tracking bit line;
• generating a negative bit line enable signal in response to that the voltage level on the first node is below a threshold voltage value of the sense circuit;
• and
• generating a negative bit line trigger signal according to the negative bit line enable signal.