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US 2022/0189538 A1Published application
Memory system
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
Estimating the term…
Abstract
A memory system includes: a normal memory area suitable for storing normal data; a security memory area suitable for storing security data; a first row hammer detection circuit suitable for sampling and counting a portion of rows that are activated in the normal memory area to select first rows that need to be refreshed; and a second row hammer detection circuit suitable for counting all rows that are activated in the security memory area to select second rows that need to be refreshed.
Claims20
A memory system, comprising:
- a normal memory area suitable for storing normal data;
- a security memory area suitable for storing security data;
- a first row hammering detection circuit suitable for sampling a portion of rows that are activated in the normal memory area and counting activation numbers of the sampled rows to select first rows to be refreshed among the sampled rows;
- and
- a second row hammering detection circuit suitable for counting activation numbers of all rows in the security memory area to select second rows to be refreshed.
2 more elements
A memory system, comprising:
- a memory including a normal area suitable for storing normal data and a security area suitable for storing security data;
- and
- a host including:
- an error correction code storing region suitable for storing an error correction code corresponding to the security data;
- and
- an error correction circuit suitable for correcting an error of data that are read from the security area based on the error correction code stored in the error correction code storing region.
3 more elements
A memory system, comprising:
- a normal memory area suitable for storing normal data;
- a security memory area suitable for storing security data;
- and
- a processor including a cache memory,
- wherein the security memory area is allowed to be accessed, by the processor, only via the cache memory.
2 more elements
A memory system, comprising:
- a normal memory area suitable for storing normal data;
- a security memory area suitable for storing security data;
- a first row hammering detection circuit suitable for sampling a portion of rows that are activated in the normal memory area and counting activation numbers of the sampled rows to select first rows to be refreshed;
- a second row hammering detection circuit suitable for counting activation numbers of all rows in the security memory area to select second rows to be refreshed;
- a cache memory suitable for storing an error correction code corresponding to the security data;
- and
- an error correction circuit suitable for correcting an error of data that are read from the security memory area based on an error correction code stored in the cache memory.
4 more elements
A memory system, comprising:
- a memory including:
- a normal area suitable for storing normal data,
- a security area suitable for storing security data, and
- a first row hammering detection circuit suitable for counting activation numbers of rows of the normal area in a random-row counting manner to detect rows to be refreshed;
- and
- a processor including:
- a second row hammering detection circuit suitable for counting activation numbers of rows of the security area in a full-row counting manner to detect rows to be refreshed.
4 more elements
Dependencies are inferred from the claim text.