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US 2022/0189535 A1Published application
Memory controller and memory system
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
Estimating the term…
Abstract
A memory controller includes: a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack; and a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to a memory per unit time according to the security level.
Claims21
A memory controller comprising:
- a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack;
- and
- a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to a memory per unit time according to the security level.
A memory controller comprising:
- a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack;
- and
- a normal refresh command control circuit suitable for controlling the number of times that a refresh command is to be applied to a memory per unit time according to the security level.
A memory system comprising:
- a memory;
- and
- a memory controller suitable for controlling the memory,
- wherein the memory controller includes:
- a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack;
- and
- a refresh management command control circuit suitable for controlling the number of times that a refresh management command is to be applied to the memory per unit time according to the security level.
4 more elements
A memory system comprising:
- a memory;
- and
- a memory controller suitable for controlling the memory,
- wherein the memory controller includes:
- a security level setting circuit suitable for setting a security level by monitoring a risk of a row hammer attack;
- and
- a normal refresh command control circuit suitable for controlling the number of times that a refresh command is to be applied to the memory per unit time according to the security level.
4 more elements
A memory system comprising:
- a memory;
- and
- a memory controller coupled to the memory and including a row hammer correspondence block configured to:
- receive active information, cache miss information, and uncorrectable error information, which are associated with an operation on the memory;
- monitor probability of a row hammering on the memory based on at least one of the received information;
- determine a security level based on the probability of the row hammering;
- and
- apply, to the memory, a command including at least one of a refresh command and a refresh management command,
- wherein a rate of applying of the command is determined based on the security level.
6 more elements
Dependencies are inferred from the claim text.