US 2022/0189534 A1 · ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION

Abstract

An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Claims27

Dependent claims

An electronic device comprising:

a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address;
and
a refresh control circuit configured to control a smart refresh operation on the target address.

A smart refresh method comprising:

performing an internal read and an internal write operation that generate a counting signal by counting the number of times each logic level combination of an address is input during an active operation;
generating a target address by generating a flag signal by comparing the counting signal and a storage counting signal, and generating a target address for performing a smart refresh operation, from the address based on the flag signal;
and
performing a smart refresh execution by performing the smart refresh operation of refreshing word lines that are adjacent to a word line, among word lines that are included in a memory region, corresponding to the target address, when a refresh command is input.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

17/521,331Filed 8 Nov 2021

Priority

KR 10-2021-009122012 Jul 2021

Published

16 Jun 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/40615
Management or control of the refreshing or charge-regeneration cycles: internal triggering or timing of refresh, e.g. hidden refresh, self…
G11C 11/40603
Management or control of the refreshing or charge-regeneration cycles: arbitration, priority and concurrent access to memory cells for read/write…
G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles

Electronic device for performing smart refresh operation

Life of this patent

Electronic device for performing smart refresh operation

Life of this patent

Abstract

Claims27