Semiconductor memory device and memory system including the same

A semiconductor memory device, comprising:

• a first latch suitable for outputting a first target address by latching an internal address according to a first target refresh command;
• a second latch suitable for outputting an active address by latching the internal address according to an active command;
• a second random sampling circuit suitable for generating sampling addresses by randomly sampling the active address;
• an output control circuit suitable for sequentially outputting the sampling addresses as a second target address according to a second target refresh command, while masking a current sampling address in response to a comparison signal;
• and
• an address select circuit suitable for outputting a final target address by selecting any of the first target address and the second target address according to the second target refresh command, and generating the comparison signal, when the first target address is the same as the second target address, by comparing the first target address with the second target address.

An operation method of a memory system, comprising:

• generating, at a memory controller, a first target address by sampling an active address according to an active command;
• providing, at the memory controller, the active address together with the active command;
• providing, at the memory controller, a first target refresh command together with the first target address;
• performing, at a memory device, a target refresh operation on at least one word line corresponding to the first target address according to the first target refresh command;
• generating, at the memory device, a second target address by sampling the active address according to the active command;
• and
• performing, at the memory device, the target refresh operation on at least one word line corresponding to the second target address according to a second target refresh command.

An operating method of a memory device, the operating method comprising:

• performing a first target refresh operation on a word line corresponding to a first target address in response to a first target refresh command, the first target address and the first target command being received from a memory controller;
• generating a second target address by sampling an active address in response to an active command;
• determining whether a number of inputs of a normal refresh command reaches a threshold;
• and
• performing a second target refresh operation on a word line corresponding to the second target address in response to the determination that the number of inputs of the normal refresh command reached the threshold.