Reconfigurable processing-in-memory logic
AssigneeMicron Technology, Inc.
InventorDmitri Yudanov
Life of this patent
Estimating the term…
Abstract
An example system implementing a processing-in-memory pipeline includes: a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; a logic array coupled to the memory array, the logic array to implement configurable logic controlling the plurality of memory cells; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of: one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
Claims20
A system, comprising:
- a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines;
- a logic array coupled to the memory array, the logic array to implement a configurable logic controlling the plurality of memory cells, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network;
- and
- a control block coupled to the memory array and the logic array, the control block to control a computational pipeline to perform computations on the data by activating at least one of:
- one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
(canceled)
A system, comprising:
- a memory array to store data in a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines, the memory array to implement configurable logic controlling the plurality of memory cells, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network;
- and
- a control block coupled to the memory array, the control block to control a computational pipeline to perform computations on the data by activating at least one of:
- one or more bitlines of the plurality of bitlines or one or more wordlines of the plurality of wordlines.
(canceled)
A method, comprising:
- implementing a configurable logic by storing data in a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines, wherein the configurable logic comprises a first pull network that is connected via a logical inverter to a second pull network;
- activating, by a control block coupled to the memory array, a selected bitline of the plurality of bitlines;
- pre-charging the selected bitline, wherein at least one wordline of the plurality of wordlines is open during the pre-charge operation;
- and
- evaluating, using the configurable logic, a row of memory cells addressed by a selected wordline.
Dependencies are inferred from the claim text.