US 2022/0189530 A1 · TERMINALS AND DATA INPUT/OUTPUT CIRCUITS LAYOUT

Abstract

Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit.

Claims20

Dependent claims

An apparatus comprising:

a memory cell array including a plurality of memory regions;
a plurality of data pads including odd numbered data pads and even numbered data pads;
and
a plurality of data queue (DQ) circuits including odd numbered DQ circuits and even numbered DQ circuits alternatingly arranged in a direction, each DQ circuit coupled between a corresponding data pad of the plurality of data pads and a corresponding memory region of the plurality of memory regions of the memory cell array,
wherein the odd numbered data pads coupled to the corresponding odd numbered DQ circuits are arranged at a side of the plurality of DQ circuits, and even numbered DQ pads coupled to the corresponding even numbered DQ circuits are arranged at an opposite side of the plurality of DQ circuits.

2 more elements

An apparatus comprising:

a first data queue (DQ) circuit configured to receive first read data on a first bus and provide the first read data, and further configured to receive first write data and provide the first write data on the first bus;
and
a first data pad configured to receive the first read data from the first DQ circuit, and further configured to receive the first write data and provide the first write data to the first DQ circuit;
a first power pad disposed across the first data pad with respect to the first DQ circuit;
a second DQ circuit adjacent to the first DQ circuit, configured to receive second read data on a second bus and provide the second read data, and further configured to receive second write data and provide the second write data on the second data bus;
and
a second data pad adjacent to the first power pad, the second data pad configured to receive the second read data from the second DQ circuit, and further configured to receive the second write data and provide the second write data to the second DQ circuit;
and
a second power pad adjacent to the first data pad and disposed across the second data pad with respect to the second DQ circuit.

6 more elements

An apparatus comprising:

first and second data queue (DQ) circuits configured to receive read data from a memory cell array and provide the read data, and further configured to receive write data and provide the write data to the memory cell array;
first and second data pad, each pad configured to receive the read data from the corresponding DQ circuit, and further configured to receive the write data and provide the write data to the corresponding DQ circuit;
first and second conductor, each conductor is configured to couple the corresponding data pad to the corresponding DQ circuit;
a first power pad adjacent to the second data pad;
and
a second power pad adjacent to the first data pad,
wherein the first data pad and the first power pad are disposed across from each other with respect to the first DQ circuit, and wherein the second data pad and the second power pad are disposed across from each other with respect to the second DQ circuit.

4 more elements

Dependencies are inferred from the claim text.

Terminals and data input/output circuits layout

Life of this patent

Terminals and data input/output circuits layout

Life of this patent

Abstract

Claims20