Wordline boost driver
AssigneeHoneywell International Inc.
InventorRobert Rabe
Life of this patent
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Abstract
An example apparatus for writing a bit to a memory cell includes wordline driver circuitry configured to generate a first voltage in response to a row access enable signal. The apparatus also includes boost driver circuitry coupled to the wordline driver circuitry. The boost driver circuitry is configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal. The apparatus also includes a wordline coupled to the memory cell and the wordline driver circuitry. The wordline is configured to output the first voltage or the second voltage to the memory cell.
Claims20
An apparatus for writing a bit to a memory cell, the apparatus comprising:
- wordline driver circuitry configured to generate a first voltage in response to a row access enable signal;
- boost driver circuitry coupled to the wordline driver circuitry and being configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal, wherein the second voltage is higher than the first voltage;
- and
- a wordline coupled to the memory cell and the wordline driver circuitry, the wordline being configured to output the first voltage or the second voltage to the memory cell,
- wherein the wordline driver circuitry comprises delay circuitry configured to output the first voltage at the wordline before expiration of a first delay from receiving the row access enable signal and to output the second voltage after expiration of a second delay from receiving the row access enable signal.
A method for writing a bit to a memory cell, the method comprising:
- generating, by wordline driver circuitry, a first voltage in response to a row access enable signal;
- charging, by boost driver circuitry, a capacitor using the first voltage:
- generating, by the boost driver circuitry, a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal, wherein the second voltage is higher than the first voltage;
- outputting, by a wordline coupled to a second memory cell and the wordline driver circuitry, the first voltage to the memory cell before expiration of a first delay from receiving the row access enable signal;
- and
- outputting, by the wordline, the second voltage to the memory cell after expiration of a second delay from receiving the row access enable signal.
A memory system comprising:
- a capacitor;
- wordline driver circuitry configured to generate a first voltage in response to a row access enable signal;
- boost driver circuitry coupled to the wordline driver circuitry and the capacitor and being configured to charge the capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor, wherein the second voltage is higher than the first voltage;
- and
- a wordline coupled to a memory cell and the wordline driver circuitry, the wordline being configured to output the first voltage or the second voltage to the memory cell,
- wherein the wordline driver circuitry comprises delay circuitry configured to output the first voltage at the wordline before expiration of a first delay from receiving the row access enable signal and to output the second voltage after expiration of a second delay from receiving the row access enable signal.
Dependencies are inferred from the claim text.