Memory system and memory module including memory chips sharing channel
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
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Abstract
A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.
Claims23
A memory system, comprising:
- a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus;
- and
- a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.
A memory module, comprising:
- a command/address bus;
- a plurality of data buses;
- and
- a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of the data buses and performing a target refresh operation according to a row-hammer address transferred through the command/address bus.
An operation method of a memory system, comprising:
- generating, at each of memory chips, a tracking address by tracking a row-hammer risk of selected banks among a plurality of banks included in each of the memory chips;
- encrypting, at each of the memory chips, the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses;
- collecting, at a memory controller, the tracking information for the banks transferred through the plurality of data buses to generate and output a row-hammer address to a command/address bus;
- and
- performing, at each of the memory chips, a target refresh operation according to the row-hammer address transferred through the command/address bus.
Dependencies are inferred from the claim text.