Multi-access memory cell

A memory device comprising:

• a first bit line;
• a second bit line;
• a source line;
• and
• an array of memory cells coupled to the first bit line, the second bit line, and the source line, wherein each of the memory cells of the array of memory cells comprises:
• a memory element being configured to store a state for a bit in response to the write operation and to output an indication of the state for the bit in response to the read operation;
• first access circuitry coupled to the first bit line, the memory element, the first access circuitry having a first transconductance, and being configured to allow a first current to flow through the first access circuitry electrically coupling the memory element to the first bit line in response to being driven in the read operation or the write operation;
• and
• second access circuitry coupled to the second bit line, and the memory element, the second access circuitry having a second transconductance, the second transconductance being different than the first transconductance, and the second access circuitry being configured to allow a second current to flow through the second access circuitry electrically coupling the memory element to the second bit line in response to being driven in the write operation and refrain from allowing the second current to flow through the second access circuitry in the read operation.

A method of operating a memory device comprising:

• applying, by a computing device, a first voltage to a first access circuitry;
• gaining access, by the computing device and in response to the application of the first voltage, to a first bit stored in a memory element through the first access circuitry, the first access circuitry being coupled to the memory element;
• reading, by the computing device, the bit stored in the memory element through a first bit line, the first bit line being coupled to the first access circuitry;
• applying, by the computing device, a second voltage to a second access circuitry;
• applying, by the computing device, a third voltage representing a second bit to a second bit line;
• gaining access, by the computing device, to the memory element through the second access circuitry, the second access circuitry being coupled to the memory element;
• writing, by the computing device, the second bit to the memory element,
• wherein the first access circuitry has a first transconductance and the second access circuitry has a second transconductance and the first transconductance is different than the second transconductance.