US 2022/0189521 A1Published application

Storage controller, storage device, and operation method of storage device

AssigneeSamsung Electronics Co., Ltd.

InventorSoon Suk HWANG

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Abstract

An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training.

Claims20

Dependent claims

An operation method of a storage device which includes a storage controller circuit and a nonvolatile memory device, the method comprising:

performing a first boot-up operation;
performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on a whole windows of the data signals;
storing offset information generated based on a result of the first training;
performing a normal operation based on the result of the first training;
performing a second boot-up operation;
performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals;
and
performing the normal operation based on a result of the second training,
wherein the detection operation includes:
sending, by the storage controller circuit, a read command and an address to the nonvolatile memory device through the plurality of data signals;
receiving, by the storage controller circuit, pattern data from the nonvolatile memory device through the plurality of data signals and a data strobe signal synchronized with the plurality of data signals;
and
when the pattern data are not matched with given reference data, adjusting, by the storage controller circuit, a delay amount of the data strobe signal.

10 more elements

A storage device comprising:

a nonvolatile memory device;
and
a storage controller circuit connected with the nonvolatile memory device through a plurality of data signals,
wherein, the storage controller circuit is configured such that, based on performing a first boot-up operation, the storage controller circuit performs first training on the plurality of data signals and generates offset information based on a result of the first training,
wherein, the storage controller circuit is further configured such that, based on performing a second boot-up operation, the storage controller circuit performs second training on the plurality of data signals within a left edge section and a right edge section of windows of the data signals, based on the offset information, and
wherein the first boot-up operation is a boot-up operation performed for a first time, and the second boot-up operation is a boot-up operation performed after the first boot-up operation.

3 more elements

A storage controller circuit comprising:

a plurality of data input/output pads configured to receive a plurality of data signals;
a data strobe pad configured to receive a data strobe signal;
and
a training circuit,
wherein the training circuit is configured such that, based on performance of a first boot-up operation, the training circuit performs first training on the plurality of data signals and generates offset information based on a result of the first training,
wherein the training circuit is further configured such that, based on performance of a second boot-up operation, the training circuit performs second training on the plurality of data signals within a left edge section and a right edge section of windows of the data signals based on the offset information, and
wherein the first boot-up operation is a boot-up operation performed for the first time, and the second boot-up operations is a boot-up operation performed after the first boot-up operation.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/523,369Filed 10 Nov 2021
Priority: KR 10-2020-017513915 Dec 2020
Published: 16 Jun 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 7/1066
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: output…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 7/1012
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data reordering during…
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…