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US 2022/0189516 A1Published application
Pipe latch circuit, operating method thereof, and semiconductor memory device including the same
AssigneeSK hynix Inc.
InventorBo Kyeom KIM
Life of this patent
Estimating the term…
Abstract
A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.
Claims16
A pipe latch circuit comprising:
- a first latching circuit group suitable for controlling a latching operation and an output operation for input data based on a plurality of pipe input control signals;
- and
- a second latching circuit group suitable for controlling a latching operation for data, output by the first latching circuit group, based on the plurality of pipe input control signals and controlling an output operation based on a plurality of pipe output control signals.
An operating method of a pipe latch circuit, comprising:
- performing, in a first pipe latching operation, a latching operation and an output operation on input data based on a plurality of pipe input control signals;
- performing, in a second pipe latching operation, a latching operation on data, output in the first pipe latching operation step, based on the plurality of pipe input control signals and performing an output operation on latched data based on a plurality of pipe output control signals;
- and
- performing, in a third pipe latching operation, a latching operation and an output operation by repeating the first pipe latching operation step and the second pipe latching operation step.
1 more element
A semiconductor memory device comprising:
- a first latching circuit group disposed within a core region and suitable for controlling a latching operation and an output operation for input data based on a plurality of pipe input control signals;
- and
- a second latching circuit group disposed within a peri region and suitable for controlling a latching operation for data that is output by the first latching circuit group, based on the plurality of pipe input control signals and controlling an output operation based on a plurality of pipe output control signals.
Dependencies are inferred from the claim text.