Memory devices including heaters

A memory device comprising:

• a three-dimensional NAND array comprising a plurality of blocks of memory cells, each block of memory cells of the plurality of blocks of memory cells comprising a plurality of NAND strings where, for each block of memory cells of the plurality of blocks of memory cells, each NAND string of the plurality of NAND strings of that block of memory cells is selectively electrically coupled between a respective data line of a plurality of data lines and a common source, and each NAND string of the plurality of NAND strings of that block of memory cells extends perpendicular to a first plane containing the common source and to a second plane containing the plurality of data lines;
• and
• a plurality of heaters, each healer of the plurality of heaters adjacent to a respective block of memory cells of the plurality of blocks of memory cells and extending perpendicular to the first plane and the second plane,
• wherein each NAND string of the plurality of NAND strings comprises a respective string of series-connected memory cells, and
• wherein each heater of the plurality of heaters comprises a first electrically conductive plate on a first side of the respective block of memory cells, a second electrically conductive plate on a second side of the respective block of memory cells parallel to the first electrically conductive plate, and a third electrically conductive plate on a third side of the respective block of memory cells extending between the first electrically conductive plate and the second electrically conductive plate.

A memory device comprising:

• a three-dimensional NAND array comprising a plurality of blocks of memory cells, each block of memory ceils of the plurality of blocks of memory cells comprising a plurality of NAND strings where, for each block of memory cells of the plurality of blocks of memory cells, each NAND string or the plurality of NAND strings of that block of memory cells is selectively electrically coupled between a respective data line of a plurality of data lines and a common source, and each NAND string of the plurality of NAND strings of that block of memory cells extends perpendicular to a first plane containing the common source, and to a second plane containing the plurality of data lines;
• and
• a plurality of heaters, each heater of the plurality of heaters adjacent to a respective block of memory cells of the plurality of blocks of memory cells and extending perpendicular to the first plane and the second plane,
• wherein each NAND string of the plurality of NAND strings comprises a respective string of series-connected memory cells, and
• wherein each heater of the plurality of heaters comprises a first plurality of electrically conductive through-array vias (TAVs) on a first side of the respective block of memory cells, a second plurality of electrically conductive TAVs on a second side of the respective block of memory cells parallel to the first plurality of electrically conductive TAVs, and a third plurality of electrically conductive TAVs on a third side of the respective block of memory cells extending between the first plurality of electrically conductive TAVs and the second plurality of electrically conductive TAVs.

A memory device comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a plurality of access lines, each access line of the plurality of access lines connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
• a heater adjacent to an end of each access line of the plurality of access lines;
• a ground node electrically coupled to a first side of the heater;
• a power supply node;
• a switch electrically coupled between the heater and the power supply node;
• and
• control logic electrically coupled to a control input of the switch, the control logic configured to turn on the switch to pass a current through the heater in response to a threshold value for the plurality of strings of series-connected memory cells being exceeded.